Silicon MOSFET scaling has become a major challenge in the semiconductor industry. Traditional techniques start to fail in reducing certain undesirable physical effects as device dimensions shrink down to the nanometer regime. For example, anti-punchthrough (APT) or halo implantation is used to reduce the short-channel effects (SCE). However, the abrupt doping profiles are difficult to achieve due to temperature enhanced diffusion, and these highly doped channels or pocket implant regions increase junction capacitance and band-to-band tunneling. It has been shown by S. Thompson, et al., in “MOS scaling: transistor challenges for the 21st century,” Intel Technology Journal, Q3, 1998, that channel engineering can only decrease the circuit gate delay by ˜10% for a given technology, and it cannot provide channel length scaling for generation after generation that gate oxide and source/drain (S/D) junction depth scaling has provided.
With bandgap engineering, an important degree of freedom can be provided in the device design. The growth of high-quality tensile strained Si/SiGe and compressively strained SiGe/Si heterostructures by molecular beam epitaxy (MBE), various types of chemical vapor deposition (CVD), and/or ion implantation allows incorporation of bandgap engineering concepts into a mature silicon technology.
Bandgap engineering has been utilized to realize various types of heterojunction field effect transistors (HFETs). The most widely studied is the modulation doped field effect transistors (MODFETs), in which a quantum well is used to confine the carriers in a lightly doped semiconductor (See K. Ismail, “Si/SiGe High-Speed Field-Effect Transistors”, IEDM, Tech. Dig., p. 509-512, 1995). Higher carrier mobility can be achieved due to reduced impurity scattering, reduced surface roughness scattering in the buried channel, and strained-induced mobility enhancement, if any, depending on the hetero material system employed. Derived from the same concept, various types of heterostructure CMOS devices have also been proposed and studied (See M. A. Armstong, et al., “Design of Si/SiGe Heterojunction Complementary Metal-Oxide Semiconductor Transistors”, IEDM Tech. Dig., p. 761-764, 1995; S. Imai et al., “Si—SiGe Semiconductor Device and Method of Fabricating the Same”, U.S. Pat. No. 5,847,419; and M. Kubo, et al., “Method of Forming HCMOS Devices with a Silicon-Germanium-Carbon compound Semiconductor Layer”, U.S. Pat. No. 6,190,975, Feb. 20, 2001.) The advantage of these devices is the higher carrier mobility and hence high drive current and high speed. However, two prominent problems remain in these planar devices: device scaling and control of short-channel effects.
As for short-channel effects, other than ultra-steep retrograded channel profiles and ultra-shallow source/drain junctions, silicon-on-insulator (SOI) has been used to control short-channel effects. However, SOI alone cannot remove the short-channel effects completely, and moreover, an inherent problem with SOI is the floating body effect. Another way to reduce the short-channel effect is to have a built-in energy barrier at the source/body junction, and in particular a barrier where the barrier height does not depend on the applied bias. The band offset provided by a heterojunction is very suitable in this case. A heterojunction MOSFET (HJMOSFET) was been proposed and studied by S. Hareland, et al., in “New structural approach for reducing punchthrough current in deep submicrometer MOSFETs and extending MOSFET scaling,” IEEE Electronics Letters, vol. 29, no. 21, pp. 1894-1896, October 1993, and by X. D. Chen, et al., in “Vertical P-MOSFETS with heterojunction between source/drain and channel,” Device Research Conference, Denver, June 2000.
Recently, a lateral, high mobility, p-channel heterojunction transistor (HMHJT) has been proposed by Q. Ouyang, et al., in U.S. Pat. No. 6,319,799. A detailed simulation study has been performed by Q. Ouyang, et al., in “A Novel Si/SiGe Heterojunction pMOSFET with Reduced Short-Channel Effects and Enhanced Drive Current,” IEEE Transactions on Electron Devices, 47 (10), 2000. In order to achieve complementary MISFETs using such a pMISFET, a comparable high performance nMISFET is needed. In the present invention, a lateral, high performance, heterojunction nMISFET is proposed and two embodiments are illustrated. Two embodiments for the complementary MOSFET are presented. The methods thereof are also described.
U.S. Pat. No. 5,285,088 describes a “High Electron Mobility Transistor”. This device has a pair of semiconductor layers for source/drain electrodes consisting of a poly SiGe layer and a poly Si layer so as to form a partially projected “overhanging-shape” over the active area. In this case, the source/drain and the gate are self-aligned. However, it is a planar structure and still suffers from the short-channel effects.